1. Field of the Invention
The present invention relates to a circuit design apparatus and a circuit design method, and more particularly to a circuit design apparatus and a circuit design method for optimizing a circuit.
2. Description of the Related Art
Conventionally, a circuit design apparatus and a circuit design method perform the logic optimization of a whole logic circuit (hereinafter called a first prior art). In the conventional logic optimization method, the whole logic circuit is manually divided into a plurality of sub-blocks and then logic optimization is performed for each sub-block (hereinafter called a second prior art).
A problem with the first prior art is that it takes long. Another problem with the first prior art is that optimization is performed in one process because a circuit is not divided into a plurality of sub-blocks.
A problem with the second prior art is that dividing a circuit into sub-blocks requires manpower. Another problem is that a target value must be set up separately for the optimization of each sub-block.
It is an object of the present invention to provide a circuit design apparatus and a circuit design method for automatically dividing a circuit to generate divided circuits.
It is another object of the present invention to provide a circuit design apparatus and a circuit design method for optimizing a circuit quickly.
According to one aspect of the present invention, a circuit design apparatus is provided which includes: a first element which divides a circuit into a plurality of divided circuits; a second element which calculates individual constraint values of the divided circuits, respectively, using a constraint value of the circuit; a third element which optimizes each of the divided circuits based on the corresponding individual constraint values; and a fourth element which merges the divided circuits, which are optimized by the third element, into one circuit.
According to another aspect of the present invention, a circuit design apparatus is provided which includes: a first element which generates a plurality of divided circuits from a circuit; a second element which selects a longest-delay-time combination out of combinations each composing of interconnected divided circuits included in the circuit, and calculates individual constraint values of the divided circuits of the selected combination using a constraint value of the circuit; a third element which optimizes the divided circuits, for which the constraint values are calculated by the second element, based on the individual constraint values; and a fourth element which merges the divided circuits optimized by the third element with the divided circuits generated by the first element but not included in the combination selected by the second element to generate one circuit.
According to another aspect of the present invention, a circuit design method is provided which includes: dividing a circuit into a plurality of divided circuits; calculating individual constraint values of the divided circuits, respectively, using a constraint value of the circuit; optimizing each of the divided circuits based on the corresponding individual constraint values; and merging the divided circuits, which are optimized during the optimizing step, into one circuit.
According to another aspect of the present invention, a circuit design method is provided which includes: generating a plurality of divided circuits from a circuit; selecting a longest-delay-time combination out of combinations each composing of interconnected divided circuits included in the circuit; calculating individual constraint values of the divided circuits of the selected combination using a constraint value of the circuit; optimizing the divided circuits, for which the constraint values are calculated, based on the individual constraint values; and merging the divided circuits included in the circuit but not in the combination selected during the selecting step with the divided circuits optimized during the optimizing step to generate one circuit.